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ADE7752/ADE7752A
POWER SUPPLY MONITOR
+ V OS × I OS + V OS × I cos ( ω t ) + I OS × V cos ( ω t )
× cos ( 2 ω t )
V × I
The ADE7752 contains an on-chip power supply monitor. The
power supply (V DD ) is continuously monitored by the ADE7752.
If the supply is less than 4 V ± 5%, the outputs of the ADE7752
are inactive. This is useful to ensure correct device startup at
power-up and power-down. The power supply monitor has
built-in hysteresis and filtering. This gives a high degree of
immunity to false triggering due to noisy supplies.
As can be seen from Figure 23, the trigger level is nominally set
at 4 V. The tolerance on this trigger level is about ±5%. The
power supply and decoupling for the part should be such that
the ripple at V DD does not exceed 5 V ± 5% as specified for
normal operation.
HPF AND OFFSET EFFECTS
Figure 25 shows the effect of offsets on the real power calcula-
tion. As can be seen, an offset on the current channel and
voltage channel contribute a dc component after multiplication.
Since this dc component is extracted by the LPF and is used to
generate the real power information for each phase, the offsets
contribute a constant error to the total real power calculation.
V DD
5V
This problem is easily avoided by the HPF in the current
channels. By removing the offset from at least one channel, no
error component can be generated at dc by the multiplication.
Error terms at cos(ωt) are removed by the LPF and the digital-
to-frequency conversion. See the Digital-to-Frequency
Conversion section.
{ V cos ( ω t ) + V OS } × { I cos ( ω t ) + I OS } =
V × I
2
+
2
The HPFs in the current channels have an associated phase
response that is compensated for on-chip. Figure 24 and
Figure 26 show the phase error between channels with the
compensation network. The ADE7752 is phase compensated
up to 1 kHz as shown. This ensures correct active harmonic
power calculation even at low power factors.
4V
V OS × I OS
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
V × I
2
0V
TIME
I OS × V
INTERNAL
RESET
INACTIVE
ACTIVE
INACTIVE
0
ω
V OS × I
2 ω
FREQUENCY – RAD/S
0.07
0.06
Figure 23. On-Chip Power Supply Monitor
Figure 25. Effect of Channel Offset on the Real Power Calculation
0.010
0.008
0.05
0.006
0.04
0.004
0.03
0.002
0.02
0.01
0
0
–0.002
–0.01
0
100
200
300
400
500
600
700
800
900 1000
–0.004
40
45
50
55 60
65
70
FREQUENCY (Hz)
Figure 24. Phase Error Between Channels (0 Hz to 1 kHz)
Rev. C | Page 17 of 24
FREQUENCY (Hz)
Figure 26. Phase Error Between Channels (40 Hz to 70 Hz)
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